Tunnel field-effect transistor

摘要

A tunnel field-effect transistor (TFET) device is provided comprising a semiconductor substrate and a fin structure disposed thereon. The fin structure comprises a channel region and a source region disposed on the channel region. The TFET further comprises a drain region contacting the channel region, wherein the source region and the drain region are of opposite conductivity type. The TFET also comprises a pocket layer covering a gate interface portion of the source region and contacting at least part of the channel region. The TFET further comprises a gate dielectric layer covering the pocket layer and a gate electrode covering the gate dielectric layer. The gate interface portion of the source region comprises at least three mutually non-coplanar surface segments. A method for manufacturing such a TFET device is also provided.

主权项

1. A tunnel field-effect transistor device, comprising:
a semiconductor substrate; a fin structure contacting the semiconductor substrate on a major surface of the semiconductor substrate, wherein the fin structure is an elevated structure with respect to the semiconductor substrate, wherein the fin structure has a height measured in a direction orthogonal to the major surface of the semiconductor substrate, wherein the fin structure has a length measured in a longitudinal direction parallel to the major surface, wherein the fin structure has a width measured in a direction orthogonal to both the direction of the height and the longitudinal direction, the fin structure comprising a channel region, a drain region, and a source region, wherein the source region is disposed on the channel region, wherein the source region comprises a gate interface portion wherein the channel region is disposed on the drain region, and wherein the source region and the drain region are of opposite conductivity type; a pocket layer covering the gate interface portion of the source region, the pocket layer contacting at least part of the channel region, wherein the gate interface portion of the source region comprises at least three mutually non-coplanar surface segments; a gate dielectric layer covering the pocket layer, the gate dielectric layer electrically isolating the gate electrode and the source region: and a gate electrode covering the gate dielectric layer, wherein the gate electrode is substantially parallel to the at least three non-coplanar surface segments, wherein the pocket layer comprises an intrinsic semiconductor material or is doped with a species opposite a conductivity type of the source region, wherein the pocket layer is configured to capture charge carriers tunneling from the source region in a direction of the gate electrode, and wherein the pocket layer is configured to divert the charge carriers via the channel region to a portion of the drain region which is in contact with the channel region but which is electrically insulated from the source region.