Efficient validation of coherency between processor cores and accelerators in computer systems

摘要

A method of testing cache coherency in a computer system design allocates different portions of a single cache line for use by accelerators and processors. The different portions of the cache line can have different sizes, and the processors and accelerators can operate in the simulation at different frequencies. The verification system can control execution of the instructions to invoke different modes of the coherency mechanism such as direct memory access or cache intervention. The invention provides a further opportunity to test any accelerator having an original function and an inverse function by allocating cache lines to generate an original function output, allocating cache lines to generate an inverse function output based on the original function output, and verifying correctness of the original and inverse functions by comparing the inverse function output to the original function input.

主权项

1. A computer system comprising:
one or more processors which process program instructions; a memory device connected to the one or more processors; and program instructions residing in the memory device for testing coherency in a system design having a shared resource, at least one processor of the one or more processors which accesses the shared resource, and at least one accelerator which accesses the shared resource, by selecting an entry of the shared resource for targeted testing during a simulation of operation of the system design, wherein the shared resource is a cache memory and the entry is a cache line of the cache memory, allocating a first portion of the selected entry for use by one or more first instructions from the at least one processor, allocating a second portion of the selected entry for use by one or more second instructions from the at least one accelerator, executing the one or more first instructions and the one or more second instructions using the allocated first and second portions of the selected entry subject to a coherency protocol adapted to maintain data consistency of the shared resource, and verifying correctness of data stored in the entry,
wherein the verifying determines that the at least one processor and the at least one accelerator can share the entry, andwherein the at least one accelerator has an original function and an inverse function which is opposite to the original function, and the program instructions further allocate a first set of entries of the shared resource for the accelerator to generate an original function output based on an original function input, allocate a second set of entries of the shared resource for the at least one accelerator to generate an inverse function output based on the original function output, and verify correctness of the original and inverse functions by comparing the inverse function output to the original function input.