| 摘要 |
PROBLEM TO BE SOLVED: To enable sampling clock control suppressing video disturbances. SOLUTION: A horizontal synchronizing circuit for generating a second horizontal synchronizing signal synchronized with a first horizontal synchronizing signal included in video signals comprises: a PLL oscillation unit for generating pixel clock signals; a phase comparison unit for outputting the difference signal of the first horizontal synchronizing signal and the second horizontal synchronizing signal; a filter for filtering the difference signal by a prescribed time constant and outputting it to the PLL oscillation unit as the correction signal of the PLL oscillation unit; a counter frequency divider for counting the pixel clock signals generated by the PLL oscillation unit and generating the second horizontal synchronizing signal by outputting a pulse signal for every prescribed number of counts; and a count control part for temporarily changing the time constant of the filter on the basis of an instruction from a user and controlling the number of counts of the counter frequency divider while the time constant is changed. COPYRIGHT: (C)2008,JPO&INPIT
|
