发明名称 |
High performance interconnect link layer |
摘要 |
Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots. |
申请公布号 |
US9444492(B2) |
申请公布日期 |
2016.09.13 |
申请号 |
US201414583542 |
申请日期 |
2014.12.26 |
申请人 |
Intel Corporation |
发明人 |
Willey Jeff;Blankenship Robert G.;Swanson Jeffrey C.;Safranek Robert J. |
分类号 |
H03M13/09;H03M13/00;G06F13/42;G06F13/00;H04L12/46 |
主分类号 |
H03M13/09 |
代理机构 |
Patent Capital Group |
代理人 |
Patent Capital Group |
主权项 |
1. An apparatus comprising:
link layer logic to:
produce a sixteen bit cyclical redundancy check (CRC) value for at least a portion of a link layer flit; andencode a sixteen bit CRC field of the flit with the CRC value, wherein the flit comprises three slots, a first of the three slots is a 72-bit slot, a second of the three slots is a 70-bit slot, a third of the three slots is an 18-bit slot, and the flit further comprises a floating payload field capable of being used to extend one of the first and second slots; and transmission logic to send the flit to a receiver. |
地址 |
Santa Clara CA US |