发明名称 Eine Schaltung und ein Verfahren zum Sichern der Verbindungssicherheit innerhalb eines Mehr-Chip-Gehäuses einer integrierten Schaltung
摘要 Circuitry implemented within a multi-chip module comprising a first integrated circuit chip and a second integrated circuit chip coupled together through an interconnect. Both the first and second integrated circuit chips include a cryptographic engine coupled to the interconnect and a non-volatile memory element used to contain key information. These cryptographic engines are solely used to encrypt outgoing information being output across the interconnect or to decrypt incoming information received from the interconnect. This prevents fraudulent physical attack of information transmitted across the interconnect.
申请公布号 DE19782075(C2) 申请公布日期 2001.11.08
申请号 DE1997182075 申请日期 1997.08.15
申请人 INTEL CORP., SANTA CLARA 发明人 DAVIS, DEREK L.
分类号 G06F1/00;G06F12/14;G06F21/00;H04L9/00;H04L9/10;(IPC1-7):H04L9/00 主分类号 G06F1/00
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