3D fin tunneling field effect transistor

摘要

A method for forming a tunneling field effect transistor includes forming gate structures over a semiconductor fin on a substrate having at least two pitches between the gate structures and recessing the fin between the gate structures. A first dielectric layer is deposited over the fin to fill in a first gap between the gate structures having a smaller pitch therebetween. A second gap between the gate structures having a larger pitch is filled with a second dielectric layer. The first gap is opened by etching the first dielectric layer while the second dielectric layer protects from opening the second gap. A source region is formed on the fin in the first gap. A dielectric fills the source region in the first gaps. The second gap is opened by etching the second dielectric layer and the first dielectric layer. A drain region is formed on the fin in the second gap.

主权项

1. A method for forming a tunneling field effect transistor, comprising:
forming gate structures over a semiconductor fin on a substrate, the gate structures having at least a first, smaller pitch between the gate structures and a second, larger pitch between the gate structures, the first, smaller pitch being over a first region of the semiconductor fin and the second, larger pitch being over a second region of the semiconductor fin; recessing the first region and the second region of the semiconductor fin between the gate structures; depositing a first dielectric layer over the semiconductor fin to fill in a first gap between the gate structures over the first region of the semiconductor fin; filling a second gap between the gate structures over the second region of the semiconductor fin with a second dielectric layer; opening the first gap by etching the first dielectric layer to expose the recessed first region of the semiconductor fin while the second dielectric layer protects from opening the second gap; forming a source region on the exposed recessed first region of the semiconductor fin in the first gap; forming a dielectric fill on the source region in the first gap; opening the second gap by etching the second dielectric layer and the first dielectric layer to expose the recessed second region of the semiconductor fin; and forming a drain region on the exposed recessed second region of the semiconductor fin in the second gap.