| 发明名称 | Memory device including memory blocks and decoders to output memory block selection signals | ||
| 摘要 | A memory device includes a plurality of memory blocks, and a row decoder including a plurality of decoders including a first decoder and a second decoder, the first decoder being configured to output a first block selection signal for selecting one of the memory blocks and a control signal for causing the second decoder to output a second block selection signal for selecting another one of the memory blocks. | ||
| 申请公布号 | US9449691(B2) | 申请公布日期 | 2016.09.20 |
| 申请号 | US201514856523 | 申请日期 | 2015.09.16 |
| 申请人 | Kabushiki Kaisha Toshiba | 发明人 | Hosono Koji;Kurosawa Tomonori |
| 分类号 | G11C16/04;G11C16/08;G11C8/12;G11C8/10;G11C8/08 | 主分类号 | G11C16/04 |
| 代理机构 | Patterson & Sheridan, LLP | 代理人 | Patterson & Sheridan, LLP |
| 主权项 | 1. A memory device comprising: a plurality of memory blocks; and a first decoder and a second decoder, the first decoder being configured to output a first block selection signal for selecting at least one of the memory blocks and a control signal for causing the second decoder to output a second block selection signal for selecting at least another one of the memory blocks. | ||
| 地址 | Tokyo JP | ||