| 摘要 |
A semiconductor device having multiple memory circuits and one or more logic sections includes a single test circuit for testing all of the memory circuits. The test circuit includes a test section that controls the memory circuits, for example, by initiating a read operation, with a control signal. Comparison/determination circuits, which correspond to the memory circuits, compare the data read from the memory circuits with expected value data, and generate determination signals. Since the various memory circuits are different distances (wire lengths) from the test section, a control section is provided which adds a delay to the control signal provided to the various memory circuits so that the memory circuits all receive the control signal at about the same time and perform their respective read operations at the same time. |
