STATIC DATA BUS ADDRESS ALLOCATION

摘要

The present invention relates to a data bus node integrated circuit comprising at least one static address selection terminal and a detecting circuit for detecting a state of the address selection terminal. The IC also comprises a communication circuit for data communication over a data bus. This circuit is adapted for determining a node address identifier taking the detected state of the at least one static address selection terminal into account. The detecting circuit is adapted for detecting the state of the address selection terminal by determining whether the address selection terminal is in a floating state, a power supply voltage state or a ground voltage state.

主权项

1. A data bus node integrated circuit comprising:
at least one static address selection terminal, a detecting circuit for detecting a state of the at least one static address selection terminal, and a communication circuit for receiving and/or transmitting data over a data bus and adapted for determining a node address identifier taking said detected state of the at least one static address selection terminal into account, wherein said detecting circuit is adapted for detecting said state of the at least one static address selection terminal by determining whether the at least one static address selection terminal is in a floating state, a power supply voltage state or a ground voltage state.