| 发明名称 |
Methods and Apparatus for Deuterium Anneal of Multi-Layered Semiconductor Structure |
| 摘要 |
Methods and apparatus for passivation of semiconductor interfaces by deuterium annealing are described. Harmonic improvements after deuterium annealing of a SOI semiconductor device with a trap-rich layer was demonstrated. Secondary ion mass spectroscopy after deuterium anneal shows a deuterium rich interface layer at the BOX-trap-rich layer interface of a MOSFET semiconductor device. |
| 申请公布号 |
US2016300729(A1) |
申请公布日期 |
2016.10.13 |
| 申请号 |
US201514683914 |
申请日期 |
2015.04.10 |
| 申请人 |
Peregrine Semiconductor Corporation |
发明人 |
Goktepeli Sinan;Hammond Richard |
| 分类号 |
H01L21/324;H01L29/06;H01L23/66;H01L29/04;H01L23/31;H01L23/29;H01L29/78;H01L29/10 |
主分类号 |
H01L21/324 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A semiconductor device comprising:
a trap-rich region; a buried oxide layer on the trap-rich region; a semiconductor layer on the buried oxide layer; and a deuterium rich region at an interface between the buried oxide layer and the trap-rich region. |
| 地址 |
San Diego CA US |
