| 主权项 |
1. A parallel computing device comprising
a plurality of nodes for executing an arithmetic process, the plurality of nodes being communicatively interconnected with each other, wherein each of the plurality of nodes includes:
a packet transmission unit that transmits a packet;a packet reception unit that receives a packet; anda processor that performs a process including:
a measurement process to measure a communication bandwidth up to a destination node based on a number of transfer devices provided on a communication path between a first node included in the plurality of nodes and a second node included in the plurality of nodes, the transfer devices each transferring a packet, the first node being a communication source, and the second node being a communication destination of the first node;a control process to control a size of a packet transmitted to the destination node according to the communication bandwidth measured by the measurement process;a transmission process to control the packet transmission unit so as to transmit, to the second node, an examination packet including a count value area for holding a count value updated by one of the transfer devices each time the examination packet passes via the one of the transfer devices; anda reception process to control the packet reception unit so as to receive a reply packet, in which the count value held in the count value area included in the examination packet is set by the second node, to the examination packet, and the measurement process obtains the number of transfer devices from the reply packet received by the reception process, and measures the communication bandwidth based on the obtained number of transfer devices. |
