| 主权项 |
1. An integrated circuit structure comprising:
a first low-k dielectric layer over a semiconductor substrate, the first low-k dielectric layer having a first upper surface and a first lower surface; a conductive wiring in the first low-k dielectric layer, the conductive wiring having a second upper surface and a second lower surface, the second upper surface substantially coplanar with the first upper surface, the second lower surface substantially coplanar with the first lower surface, the conductive wiring having a first sidewall opposing a second sidewall, a first portion of the first low-k dielectric layer adjacent to the first sidewall, a second portion of the first low-k dielectric layer adjacent to the second sidewall, the first low-k dielectric layer comprising a first substantially homogeneous material; a metal carbide cap layer over the conductive wiring; a second low-k dielectric layer over the metal carbide cap layer; and a conductive via in the second low-k dielectric layer, the conductive via having a third sidewall opposing a fourth sidewall; wherein:
the conductive via penetrates an opening in the metal carbide cap layer;a contact portion of the conductive via is in physical contact with the conductive wiring, the contact portion of the conductive via comprising a material that is different than material of the metal carbide cap layer;the third sidewall is disposed in and adjacent to the second low-k dielectric layer;the fourth sidewall is disposed in and adjacent to the second low-k dielectric layer;the second low-k dielectric layer comprises a second substantially homogeneous material;a contact interface between the first low-k dielectric layer and the second low-k dielectric layer does not comprise an etch stop layer;the first low-k dielectric layer has a first dielectric constant of less than about 3.0; andthe second low-k dielectric layer has a second dielectric constant of less than about 3.0. |
