发明名称 Fully depleted region for reduced parasitic capacitance between a poly-silicon layer and a substrate region
摘要 The structure includes doped regions 204A & 204B to form a fully depleted region 214 based on lateral interaction of dopant in the doped regions and the substrate region. A fully depleted region is formed below a device 210 to reduce device to substrate parasitic capacitance. An additional parasitic capacitance is formed between the fully depleted region and the substrate. This additional parasitic capacitance is coupled in series with a first parasitic capacitance between a poly-silicon layer of the electronic device and the doped region. The series combination of the first parasitic capacitance and the additional parasitic capacitance results in an overall reduction of parasitic capacitance experience by the electronic device (eg a MEMS microphone).
申请公布号 GB2534458(A) 申请公布日期 2016.07.27
申请号 GB20150020363 申请日期 2015.11.19
申请人 Cirrus Logic, Inc. 发明人 Shanjen Pan;Marc L Tarabbia
分类号 H01L21/76;B81B3/00;H04R19/04 主分类号 H01L21/76
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