| 摘要 |
Decoder circuitry for an input channel having a data rate, where a codeword on the input channel includes a plurality of symbols, includes options to provide a first output channel having that data rate, and a plurality of second output channels having slower data rates. The decoder circuitry includes syndrome calculation circuitry, polynomial calculation circuitry, and search-and-correct circuitry. The syndrome calculation circuitry includes finite-field multipliers for multiplying each symbol by a power of a root of the field. Each multiplier other than a first multiplier multiplies a symbol by a higher power of the root than an adjacent multiplier. First-level adders add outputs of a number of groups of multipliers. A second-level adder adds outputs of the first-level adders to be accumulated as syndromes of the first output channel. Another plurality of accumulators accumulates outputs of the first-level adders, which after scaling, are syndromes of the second output channels. |
| 主权项 |
1. Decoder circuitry for an input channel having a first data rate, a codeword on said input channel including a plurality of symbols, wherein:
said decoder channel includes both an option to provide a first output channel having said first data rate and an option to provide a plurality of second output channels having data rates less than said first data rate; said decoder circuitry comprises syndrome calculation circuitry, polynomial calculation circuitry, and search-and-correct circuitry; and said syndrome calculation circuitry comprises: a plurality of finite-field multipliers corresponding in number to said plurality of symbols for multiplying said symbols by a power of a root of said finite field, each respective multiplier in said plurality of multipliers, other than a first multiplier, multiplying a respective symbol in said plurality of symbols by a higher power of said root than an adjacent multiplier in said plurality of multipliers, first-level adder circuitry for adding outputs of a number of groups of multipliers in said plurality of multipliers, a second-level adder for adding outputs of said first-level adder circuitry, a first accumulator for accumulating outputs of said second-level adder as syndromes of said first output channel, a plurality of second accumulators equal in number to said groups of multipliers for accumulating outputs of said first-level adder circuitry, and a respective scaling multiplier for all but one of said second accumulators, whereby an output of each of said second accumulators is a syndrome of one of said second output channels. |
