| 摘要 |
Delay lock loops, signal locking methods, and methods of implementing delay lock loops are described. In one embodiment, a delay lock loop comprises a delay line having first and second inputs and an output. The first input is configured to receive a clock signal. An output model has an input and an output, with the input being operably coupled with the delay line output. The output model is configured to model delays in a system which can be driven by an output clock signal produced by the delay lock loop. A phase detector has a pair of inputs and an output. Phase detector's output is operably coupled with the second input of the delay line. A delay element is interposed between and operably couples both the (a) output of the output model, and (b) the clock signal received by the delay line, with respective inputs of the phase detector. The delay element is configured to present an additional delay to the phase detector which is in addition to the modeled delay provided by the output model. Other embodiments are described.
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