| 摘要 |
A data output circuit includes a first trigger unit and a signal generation unit. The first trigger unit is inputted with first data in a first mode and a second mode, and outputs the first data in response to a first trigger signal. The signal generation unit, in the first mode, outputs the first trigger signal in response to a first clock signal, and, in the second mode, retains the first trigger signal in a first state regardless of the first clock signal. |
| 主权项 |
1. A data output circuit comprising:
a first trigger unit configured to be inputted with first data in a first mode and a second mode, and output the first data in response to a first trigger signal; and a signal generation unit configured to, in the first mode, output the first trigger signal in response to a first clock signal, and, in the second mode, retain the first trigger signal in a first state regardless of the first clock signal. |
