| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a technique capable of ensuring the withstand voltage of a semiconductor device. <P>SOLUTION: A sealing body 4 seals a first inner portion 1A, a first offset portion 1C, and a part of a first outer portion 1B of a first lead 1, and seals a second inner portion 2A, a second offset portion 2C, and a part of a second outer portion 2B of a second lead 2. Furthermore, the first outer portion 1B has a first rear surface D11 exposed from the lower surface of the sealing body 4, a first outer end surface D12 orthogonal to the extending direction of the first lead 1, and a first inner end surface D13 located at the boundary between the first offset portion 1C and the first outer portion 1B. The second outer portion 2B has a second rear surface D21 exposed from the lower surface of the sealing body 4, a second outer end surface D22 orthogonal to the extending direction of the second lead 2, and a second inner end surface D23 located at the boundary between the second offset portion 2C and the second outer portion 2B. <P>COPYRIGHT: (C)2012,JPO&INPIT |
