SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

摘要

PROBLEM TO BE SOLVED: To reduce input skew of a logic integrated circuit device provided with a number of input pins without deteriorating the use efficiency of a user logic part, and improve speed and to speed up the machine cycle of a computer system. SOLUTION: In the logic integrated circuit device, such as ASICs which is provided with a number of input pins PAD and an input circuit IC1, an input delay circuit DL which selectively switches transmission delay time of an input signal DIN1 in accordance with delay control signals C1 to Ci and an automatic delay control circuit ADLC, which selectively becomes goes into operation state at switching of power on and at resetting and generates the delay control signals C1 to Ci, so as to set the transmission delay time of the corresponding input delay circuit DL to a prescribed value are installed in each of the input circuits IC1. An input/output cell is constituted on the basis of the input circuit IC1 containing both of the input delay circuit DL and the automatic delay control circuit ADLC and a corresponding output circuit. The cells are arranged along the four sides of a semiconductor substrate face, where the logic integrated circuit devices are formed.