CLOCK DATA RECOVERY CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a clock data recovery circuit which can autonomously and correctly be locked to serial data with very simple circuit constitution and performs stable recovery operation. SOLUTION: The clock data recovery circuit 10 which uses a PLL circuit 19 as a means for generating a clock according to inputted NRZ data and oscillates a VCO 17 by using a reference clock RCK to prelock the PLL circuit 19 to the reference clock and then lock it to the NRZ data is provided with a 1st lock detector 21 which detects the PLL circuit being locked to the reference clock RCK and a 2nd lock detector 22 which detects the PLL circuit not being locked to the NRZ data, and properly switch control based upon the reference clock RCK and control based upon the NRZ data by a selector 13 according to the detection outputs of the detectors.