发明名称 Methods and apparatus to program multi-level cell memory using target-only verify
摘要 A disclosed example includes selectively precharging first bitlines of first multi-level cell (MLC) memory cells of a wordline without precharging second bitlines of second MLC memory cells of the wordline during a program verify. First strobe state outputs of the first MLC memory cells are obtained based on first sensed threshold voltage levels of the first MLC memory cells sensed at a first time. Second strobe state outputs of the first MLC memory cells are obtained based on second sensed threshold voltage levels of the first MLC memory cells sensed at a second time. Based on the first and second strobe state outputs, a first MLC memory cell of the first MLC memory cells is programmed using a first programming pulse, and a second MLC memory cell of the first MLC memory cells is programmed using a second programming pulse having a relatively higher voltage than the first programming pulse.
申请公布号 US9478305(B1) 申请公布日期 2016.10.25
申请号 US201514851479 申请日期 2015.09.11
申请人 Intel Corporation 发明人 Srinivasan Dheeraj
分类号 G11C16/04;G11C16/34;G11C11/56;G11C16/24;G11C16/26 主分类号 G11C16/04
代理机构 Hanley, Flight & Zimmerman, LLC 代理人 Hanley, Flight & Zimmerman, LLC
主权项 1. A method to program a multi-level cell (MLC) memory, the method comprising: during a program verify process: selectively precharging first bitlines of first MLC memory cells of a wordline without precharging second bitlines of second MLC memory cells of the wordline; obtaining first strobe state outputs of the first MLC memory cells, the first strobe state outputs based on first sensed threshold voltage levels of the first MLC memory cells sensed at a first time; and obtaining second strobe state outputs of the first MLC memory cells, the second strobe state outputs based on second sensed threshold voltage levels of the first MLC memory cells sensed at a second time; andbased on the first and second strobe state outputs, programming a first MLC memory cell of the first MLC memory cells using a first programming pulse, and programming a second MLC memory cell of the first MLC memory cells using a second programming pulse having a relatively higher voltage than the first programming pulse.
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