DATA ACQUISITION MODULE AND METHOD, DATA PROCESSING UNIT, DRIVER AND DISPLAY DEVICE

摘要

The present invention provides a data acquiring module, comprising: a data input and output terminal, through which date enter into the data acquiring module, and which can output data independently; a shift register groups, each of which comprises (b−1) serially connected shift registers, and an output terminal of each shift register being able to output data independently, wherein a and b are integers greater than 1; and (a−1) serially connected first-in first-out memories connected to (a−1) shift register groups respectively, and the output terminal of each first-in first-out memory being able to output data independently, an input terminal of the last shift register in the shift register group without a corresponding first-in first-out memory in the a shift register groups, and the input terminal of the last first-in first-out memory of the serially connected first-in first-out memories being connected to the data input and output terminal. The present invention also provides a data processing unit, a driver and a display device.

主权项

1. A data acquiring module, comprising:
a data input and output terminal, through which data enter into the data acquiring module, and which can output data independently; a shift register groups, each of which comprises (b−1) serially connected shift registers, an output terminal of each shift register being able to output data independently, wherein a and b are integers greater than 1; and (a−1) serially connected first-in first-out memory corresponding to (a−1) shift register groups respectively, an output terminal of each of the first-in first-out memories being connected to the input terminal of the last shift register in the corresponding shift register group, and the output terminal of each of the first-in first-out memories being able to output data independently; an input terminal of the last shift register in the shift register group without a corresponding first-in first-out memory in the a shift register groups, and an input terminal of the last first-in first-out memory in the (a−1) serially connected first-in first-out memories being connected to the data input and output terminal.