| 摘要 |
A clock input circuit is provided to minimize delay time between an external clock signal and an internal clock signal and duty cycle variation width of the internal clock signal. A first clock buffer part(10) generates a first clock signal by amplifying an external clock signal and a first reference voltage signal differentially. A second clock buffer part(20) generates a second clock signal by amplifying the external clock signal and a second reference voltage signal differentially. A driver part(40) generates an internal clock signal in response to the first clock signal and the second clock signal. The first reference voltage signal is an external reference voltage signal set in the outside. The second reference voltage signal is generated from a bandgap reference voltage generator(30).
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