| 摘要 |
This memory device system is provided with a first memory (1), a second memory (2), a first register (3), a second register (4), a comparator (5), a transfer register (6), an error data register (7), an error address register (8), a parity calculation unit (9), and a control unit (10). If the parity calculation unit determines that there is a parity match, the control unit causes the transfer register to transmit all the data stored in the transfer register to an external circuit (12). If the parity calculation unit determines that there is no parity match, then the control unit replaces the data at the address stored in the error address register with the data stored in the error data register, then causes the parity calculation unit to determine again whether there is a parity match, and causes the transfer register to transmit all the data stored in the transfer register to the external circuit if the parity calculation unit determines that there is a parity match. |
