Verification Log Analysis

摘要

A verification log analyzer graphically represents a log file generated from a simulation. The log analyzer depicts the log file visually and/or graphically, for example, in the form of a bar graph or timeline. The bar graph can include one axis (e.g., the x-axis) that represents the time of the simulation, with various events/messages displayed as graphics along the timeline. The timeline can include a series of bars, boxes, icons, images, or other identifiers that represent messages from the verification log. The log analyzer can expand, collapse, zoom in, and zoom out on the graphical log file. The log analyzer can also add, remove, or restrict information provided by the graphical log file.

主权项

1) A method of generating a graphical representation of a log file from a simulation for display on a user interface, the method comprising:
generating a verification log file based on a simulated test of a modeled integrated circuit using a computer processor configured to execute test simulation code; and displaying a graphical model of the verification log file on the user interface, the graphical model comprising at least one bar chart displayed on a user interface that operates in connection with the processor, the bar chart comprising a horizontal axis that represents time elapsed during the simulated test of the modeled integrated circuit and at least one bar along the x-axis, the bar representing a message of the verification log file.