发明名称 NETWORK TOPOLOGY FOR A SCALABLE MULTIPROCESSOR SYSTEM
摘要 A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters.
申请公布号 US2016337229(A1) 申请公布日期 2016.11.17
申请号 US201615220189 申请日期 2016.07.26
申请人 SILICON GRAPHICS INTERNATIONAL CORP. 发明人 Deneroff Martin M.;Thorson Gregory M.;Passint Randal S.
分类号 H04L12/721;H04L29/08 主分类号 H04L12/721
代理机构 代理人
主权项 1. A system for routing information in a computing network, the system comprising: a plurality of computing clusters; and a plurality of high speed routers, wherein the plurality of high speed routers include at least four ports, and the plurality of high speed routers connect each respective computing cluster of the plurality of computing clusters with each other respective computing cluster of the plurality of computing clusters such that communications between two respective computing clusters of the plurality of computing clusters do not travel through a third computing cluster.
地址 Milpitas CA US