DISPLAY DEVICE AND DRIVING METHOD THEREOF

摘要

A display device includes a display unit including a light emitting device, data and gate driver for respectively applying data and gate voltages to the display unit, and a signal controller for transmitting, to the data driver, image data having a clock embedded therein. The data driver recovers a first internal reference clock during a low period of a first frame control signal, using the image data having the clock embedded therein, compares the frequency of the recovered first internal reference clock with the frequency of a previously stored reference clock, when the frequency of the recovered first internal reference clock is within an error range of the frequency of the previously stored reference clock, outputs the recovered first internal reference clock and receives a second frame control signal, and when the second frame control signal corresponds to a CDR unit operating condition, recovers a second internal reference clock.

主权项

1. A display device comprising:
a display unit configured to display an image using a light emitting device; a signal controller configured to transmit an image signal and a control signal, the image signal is embedded with a clock signal; a data driver comprising a clock data recovery (CDR) unit that extracts from the image signal a first internal reference clock signal during an inactive period of a first frame control signal; a memory that stores the frequency of a preset reference clock signal; a comparator that compares the frequency of the recovered first internal reference clock signal with the frequency of the preset reference clock signal, wherein when the frequency of the recovered first internal reference clock signal is within an error range of the frequency of the preset reference clock signal, outputs the recovered first internal reference clock signal, and receives a second frame control signal, and when the second frame control signal corresponds to a previously set CDR unit operating condition, recovers a second internal reference clock signal.