Apparatus and Method for a Low Loss Coupling Capacitor

摘要

Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

主权项

1. A circuit structure for a coupling capacitor comprising:
a p-doped semiconductor substrate (Psub); a deep n-doped semiconductor well (DNW) in the Psub; a p-doped semiconductor well (P well) in the DNW; a first block of a p-doped semiconductor material extending from a surface of the P well into the P well, wherein the first block is a source terminal; a second block of the p-doped semiconductor material extending from the surface of the P well into the P well, wherein the second block is a drain terminal; an insulator block on the P well between the source terminal and the drain terminal; a block of conductor material on the insulator block between the source terminal and the drain terminal, wherein the block of conductor material is a gate; and a metal pattern comprising a plurality of layers of metal lines wherein the layers of metal lines are approximately parallel to the surface, and a plurality of vias through the metal lines and perpendicular to the metal lines, wherein the vias connect the metal lines to the gate, the source terminal, and the drain terminal.