Data loading circuit and semiconductor memory device comprising same

摘要

A data loading circuit comprises a non-volatile memory configured to store non-volatile data and output a serial data signal based on the stored non-volatile data in response to a power-up operation, a deserializer configured to receive the serial data signal and output multiple data bits at intervals of a unit period based on the received serial data signal, a load controller configured to generate multiple loading selection signals that are sequentially activated one-by-one at each interval of the unit period, and a loading memory unit configured to sequentially store the data bits at each interval of the unit period in response to the loading selection signals.

主权项

1. A semiconductor memory device, comprising:
a memory cell array comprising normal memory cells coupled to normal selection lines and redundancy memory cells coupled to redundancy selection lines; a decoder configured to select one of the normal selection lines based on an address of a read operation or a write operation; a non-volatile memory configured to store fail addresses indicating locations of fail memory cells among the normal memory cells, and further configured to output a serial data signal based on the stored fail addresses in response to a power-up operation; a load controller configured to generate multiple loading selection signals that are sequentially activated one-by-one at intervals of a unit period; and a repair control circuit configured to store the fail addresses sequentially based on the serial data signal and the loading selection signals, and further configured to select one of the redundancy selection lines with disabling the decoder when the address is identical to one of the stored fail addresses.