发明名称 |
Nonvolatile semiconductor memory with dual latch sense amplifier |
摘要 |
A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value. |
申请公布号 |
US9384848(B2) |
申请公布日期 |
2016.07.05 |
申请号 |
US201414263948 |
申请日期 |
2014.04.28 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
Iwai Makoto;Nakamura Hiroshi |
分类号 |
G11C16/04;G11C16/34;G11C11/56;G11C16/26;G11C16/06 |
主分类号 |
G11C16/04 |
代理机构 |
Oblon, McClelland, Maier & Neustadt, L.L.P. |
代理人 |
Oblon, McClelland, Maier & Neustadt, L.L.P. |
主权项 |
1. A nonvolatile semiconductor memory comprising:
a first transistor; a second transistor; a memory cell unit including memory cells coupled in series; word lines coupled to gates of the memory cells; a sense amplifier including a first node, a third transistor, a fourth transistor and a first capacitor, a first terminal of the third transistor being coupled to the first node, a first terminal of the fourth transistor being coupled to both the first node and the first terminal of the third transistor, and a first terminal of the first capacitor being coupled to the first node; and a controller configured to perform a verify operation including a first operation and a second operation, to apply a first voltage to a gate of the fourth transistor and apply a second voltage to a gate of the third transistor in the first operation, to apply a third voltage to the gate of the fourth transistor and apply a fourth voltage to the gate of the third transistor in the second operation, and to perform the first operation and the second operation during applying a verify voltage to a first word line selected from the word lines, the second voltage being higher than the first voltage and the fourth voltage being higher than the third voltage. |
地址 |
Minato-ku JP |