CYCLE ACCURATE STATE ANALYSIS WITH PROGRAMMABLE TRIGGER LOGIC

摘要

In one embodiment, cycle-accurate information may be collected by stopping an input clock associated with a functional block of a SoC using a programmable trigger signal. The programmable trigger signal may also stops a root clock of the SoC. Cycle-accurate information may be collected regarding the functional block and at least one other functional block of the SoC at the time of the programmable trigger signal. The collected information may be outputted and used to debug the SoC in a time-efficient manner.

主权项

1. A method, comprising:
stopping an input clock associated with a functional block of a System on a Chip (SoC) using a programmable trigger signal, wherein the programmable trigger signal also stops a root clock of the SoC; collecting information regarding the functional block and at least one other functional block of the SoC at the time of the programmable trigger signal; and outputting, to host for analysis, the information regarding the functional block and the at least one other functional block of the SoC at the time of the programmable trigger signal.