NEURON PERIPHERAL CIRCUITS FOR NEUROMORPHIC SYNAPTIC MEMORY ARRAY BASED ON NEURON MODELS

摘要

A neuromorphic memory system including neuromorphic memory arrays. Each neuromorphic memory array includes rows and columns of neuromorphic memory cells. A column of postsynaptic circuits is electrically coupled to postsynaptic spike timing dependent plasticity (STDP) lines. Each postsynaptic STDP line is coupled to a row of neuromorphic memory cells. A column of summing circuits is electrically coupled to postsynaptic leaky integrate and fire (LIF) lines. Each postsynaptic LIF line is coupled to the row of neuromorphic memory cells at a respective memory array. Each summing circuit provides a sum of signals from the postsynaptic LIF lines to a respective postsynaptic circuit.

主权项

1. A neuromorphic memory system comprising:
a plurality of neuromorphic memory arrays, each of the neuromorphic memory arrays including rows and columns of neuromorphic memory cells; a column of postsynaptic circuits, each of the postsynaptic circuits electrically coupled to a plurality of postsynaptic spike timing dependent plasticity (STDP) lines, each of the postsynaptic STDP lines coupled to a row of neuromorphic memory cells at a respective memory array of the memory arrays; a column of summing circuits, each of the summing circuits electrically coupled to a plurality of postsynaptic leaky integrate and fire (LIF) lines, each of the postsynaptic LIF lines coupled to the row of neuromorphic memory cells at the respective memory array, each of the summing circuits providing a sum of signals from the postsynaptic LIF lines to a respective postsynaptic circuit of the postsynaptic circuits.