Method and apparatus for cutting senior store latency using store prefetching

摘要

In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for cutting senior store latency using store prefetching. For example, in one embodiment, such means may include an integrated circuit or an out of order processor means that processes out of order instructions and enforces in-order requirements for a cache. Such an integrated circuit or out of order processor means further includes means for receiving a store instruction; means for performing address generation and translation for the store instruction to calculate a physical address of the memory to be accessed by the store instruction; and means for executing a pre-fetch for a cache line based on the store instruction and the calculated physical address before the store instruction retires.

主权项

1. A method comprising:
receiving an instruction, wherein the received instruction is a store instruction, at an out-of-order processor, wherein the out-of-order processor enforces in-order requirements for a cache; performing address generation and translation for the store instruction to calculate a physical address of the memory to be accessed by the store instruction; and in response to the received instruction being the store instruction, executing a pre-fetch operation for a cache line data based on the store instruction and for the same calculated physical address while the store instruction is pending and before the store instruction retires.