| 发明名称 |
MEMORY SCANNING METHODS AND APPARATUS |
| 摘要 |
Memory scanning methods and apparatus are disclosed. An example apparatus includes a walker to traverse a paging structure of an address translation system; a bit analyzer to determine whether a bit associated with an entry of the paging structure is indicative of the entry being recently accessed; an address identifier to, when the bit analyzer determines that the bit associated with the entry of the paging structure is indicative of the entry being recently accessed, determine an address associated with the entry; and an outputter to provide the determined address to a memory scanner. |
| 申请公布号 |
US2016283717(A1) |
申请公布日期 |
2016.09.29 |
| 申请号 |
US201514671764 |
申请日期 |
2015.03.27 |
| 申请人 |
Intel Corporation |
发明人 |
LeMay Michael;Durham David M.;Long Men |
| 分类号 |
G06F21/56;G06F12/10;G06F12/08 |
主分类号 |
G06F21/56 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus, comprising:
a walker to traverse a paging structure of an address translation system; a bit analyzer to determine whether a bit associated with an entry of the paging structure is indicative of the entry being recently accessed; an address identifier to, when the bit analyzer determines that the bit associated with the entry of the paging structure is indicative of the entry being recently accessed, determine an address associated with the entry; and an outputter to provide the determined address to a memory scanner, wherein at least one of the walker, the bit analyzer, the address identifier, or the outputter is implemented via a logic circuit. |
| 地址 |
Santa Clara CA US |
