| 摘要 |
A pillar-shaped semiconductor memory device includes Si pillars arranged in at least two rows; a tunnel insulating layer; a data charge storage insulating layer; first, second, and third interlayer insulating layers; and first and second conductor layers, all of which surround outer peripheries of the Si pillars, the first and second conductor layers being located at the same height in a perpendicular direction. A row of the semiconductor pillars is interposed between the first and second conductor layers of Si pillars arranged in an X direction. Shapes of the first and second conductor layers facing the semiconductor pillars are circular arcs. Adjacent circular arcs of the first conductor layer are in contact with each other, and adjacent circular arcs of the second conductor layer are in contact with each other. A pitch length of the Si pillars in the X direction is smaller than that in a Y direction. |
| 主权项 |
1. A pillar-shaped semiconductor memory device comprising:
a semiconductor substrate; semiconductor pillars disposed on the semiconductor substrate, extending in a direction perpendicular to a surface of the semiconductor substrate, and arranged in at least two rows; a tunnel insulating layer surrounding an outer periphery of each of the semiconductor pillars; a data charge storage insulating layer surrounding an outer periphery of the tunnel insulating layer; a first interlayer insulating layer surrounding an outer periphery of the data charge storage insulating layer; and a first stacked material layer and a second stacked material layer that are disposed on the semiconductor substrate so that one row of the semiconductor pillars is interposed between the first stacked material layer and a second stacked material layer, the first stacked material layer being at least one laminate including, as one set,
a first conductor layer surrounding a part of an outer periphery of the first interlayer insulating layer of the semiconductor pillars arranged in the one row, anda second interlayer insulating layer formed on or under the first conductor layer, and the second stacked material layer being at least one laminate including, as one set,
a second conductor layer surrounding another part of the outer periphery of the first interlayer insulating layer of the semiconductor pillars arranged in the one row, and disposed at the same position as that of the first conductor layer in the direction perpendicular to the surface of the semiconductor substrate, anda third interlayer insulating layer formed on or under the second conductor layer, wherein a pitch length between semiconductor pillars adjacent to each other in the one row of the semiconductor pillars is smaller than a pitch length between a semiconductor pillar in the one row and a semiconductor pillar in a row other than the one row, in plan view, shapes of the first conductor layer and the second conductor layer, the shapes facing the semiconductor pillars, are circular arc shapes, and, between the semiconductor pillars adjacent to each other, the circular arcs of the first conductor layer are in contact with each other and the circular arcs of the second conductor layer are in contact with each other, in plan view, the first interlayer insulating layer is disposed between a contact point of the circular arcs of the first conductor layer and a contact point of the circular arcs of the second conductor layer, and data writing and erasing due to a data charge transfer between the semiconductor pillars and the data charge storage insulating layer through the tunnel insulating layer or a data charge retention by the data charge storage insulating layer is performed by application of a voltage to the first conductor layer and the second conductor layer. |
