| 摘要 |
PROBLEM TO BE SOLVED: To provide a level shifter circuit for preventing the occurrence of a through-current only with a CMOS gate. SOLUTION: A NOR gate 22 and an AND gate 23, to which a low level voltage VDDL of a first power supply voltage is applied, receive an input signal Vin from an input terminal 50 and an input signal Vin' delayed by a delay section 21 and provide outputs of gate voltages VG1 and VG2. Gates and drains of PMOS transistors 1, 2 connected to a second power supply voltage terminal 30, to which a high level voltage VDDH of a second power supply voltage is applied, are cross-connected to each other respectively in a level shift section 10, and the drains of which are respectively connected to drains of NMOS transistors 4, 5 connected to a ground terminal 40. An output of the NOR gate 22 and an output of the AND gate 23 are connected to the gates of the NMOS transistors 4, 5, respectively. A drain voltage VD2 of the NMOS transistor 5 is given to gates of a PMOS transistor 3 and an NMOS transistor 6 and an Vout is output from an output terminal 70. COPYRIGHT: (C)2006,JPO&NCIPI
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