Self-compensating gate driving circuit

摘要

The present invention provides a self-compensating gate driving circuit, comprising: a plurality of GOA units which are cascade connected, and a Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area, and the Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area, and the Nth GOA unit comprises a pull-up controlling part, a pull-up part, a transmission part, a first pull-down part, a bootstrap capacitor part and a pull-down holding part; the pull-up part, the first pull-down part, the bootstrap capacitor part and the pull-down holding circuit are respectively coupled to a Nth gate signal point Q(N) and the Nth horizontal scanning line G(n), and the pull-up controlling part and the transmission part are respectively coupled to the Nth gate signal point Q(N), and the pull-down holding part is inputted with a DC low voltage VSS; the pull-down holding part comprises a first pull-down holding part and a second pull-down holding part to alternately work. The present invention is designed to have the pull-down holding part with self-compensating function to promote the reliability of the long term operation for the gate driving circuit. The influence of the threshold voltage drift to the operation of the gate driving circuit is diminished.

主权项

1. A self-compensating gate driving circuit, comprising: a plurality of gate driver on array units which are cascade connected, and a Nth gate driver on array unit controls charge to a Nth horizontal scanning line in a display area, and the Nth gate driver on array unit comprises a pull-up controlling part, a pull-up part, a transmission part, a first pull-down part, a bootstrap capacitor part and a pull-down holding part; the pull-up part, the first pull-down part, the bootstrap capacitor part and the pull-down holding circuit are respectively coupled to a Nth gate signal point and the Nth horizontal scanning line, and the pull-up controlling part and the transmission part are respectively coupled to the Nth gate signal point, and the pull-down holding part is inputted with a DC low voltage;
the pull-down holding part comprises a first pull-down holding part and a second pull-down holding part to alternately work; the first pull-down holding part comprises: a first thin film transistor, and a gate of the first thin film transistor is electrically coupled to the first circuit point, and a drain is electrically coupled to the Nth horizontal scanning line, and a source is inputted with the DC low voltage; a second thin film transistor, and a gate of the second thin film transistor is electrically coupled to the first circuit point, and a drain is electrically coupled to the Nth gate signal point, and a source is inputted with the DC low voltage; a third thin film transistor, and a gate of the third thin film transistor is electrically coupled to a first low frequency clock or a first high frequency clock, and a drain is electrically coupled to a first low frequency clock or a first high frequency clock, and a source is electrically coupled to a second circuit point; a fourth thin film transistor, and a gate of the fourth thin film transistor is electrically coupled to the Nth gate signal point, and a drain is electrically coupled to the second circuit point, and a source is inputted with the DC low voltage; a fifth thin film transistor, and a gate of the fifth thin film transistor is electrically coupled to a N−1th transmission signal, a drain is electrically coupled to the first circuit point, and a source is inputted with the DC low voltage; a sixth thin film transistor, and a gate of the sixth thin film transistor is electrically coupled to a N+1th horizontal scan line, and a drain is electrically coupled to the first circuit point, and a source is electrically coupled to the Nth gate signal point; a seventh thin film transistor, and a gate of the seventh thin film transistor is electrically coupled to a second low frequency clock or a second high frequency clock, and a drain is a first low frequency clock or a first high frequency clock, and a source is electrically coupled to the second circuit point; an eighth thin film transistor, and a gate of the eighth thin film transistor is electrically coupled to a Nth transmission signal, and a drain is electrically coupled to the first circuit point, and a source is inputted with the DC low voltage; a first capacitor, and an upper electrode plate of the first capacitor is electrically coupled to the second circuit point and a lower electrode plate of the first capacitor is electrically coupled to the first circuit point; the second pull-down holding part comprises: a ninth thin film transistor, and a gate of the ninth thin film transistor is electrically coupled to the third circuit point, and a drain is electrically coupled to the Nth horizontal scanning line, and a source is inputted with the DC low voltage; a tenth thin film transistor, and a gate of the tenth thin film transistor is electrically coupled to the third circuit point, and a drain is electrically coupled to the Nth gate signal point, and a source is inputted with the DC low voltage; an eleventh thin film transistor, and a gate of the eleventh thin film transistor is electrically coupled to a second low frequency clock or a second high frequency clock, and a drain is electrically coupled to a second low frequency clock or a second high frequency clock, and a source is electrically coupled to a fourth circuit point; a twelfth thin film transistor, and a gate of the twelfth thin film transistor is electrically coupled to the Nth gate signal point, and a drain is electrically coupled to the fourth circuit point, and a source is inputted with the DC low voltage; a thirteenth thin film transistor, and a gate of the thirteenth thin film transistor is electrically coupled to a N−1th transmission signal, a drain is electrically coupled to the third circuit point, and a source is inputted with the DC low voltage; a fourteenth thin film transistor, and a gate of the fourteenth thin film transistor is electrically coupled to a N+1th horizontal scan line, and a drain is electrically coupled to the third circuit point, and a source is electrically coupled to the Nth gate signal point; a fifteenth thin film transistor, and a gate of the fifteenth thin film transistor is electrically coupled to a first low frequency clock or a first high frequency clock, and a drain is a second low frequency clock or a second high frequency clock, and a source is electrically coupled to the fourth circuit point; a sixteenth thin film transistor, and a gate of the sixteenth thin film transistor is electrically coupled to the Nth transmission signal, and a drain is electrically coupled to the third circuit point, and a source is inputted with the DC low voltage; a second capacitor, and an upper electrode plate of the second capacitor is electrically coupled to the fourth circuit point and a lower electrode plate of the second capacitor is electrically coupled to the third circuit point.