GaN-On-Silicon (GOS) structures and techniques for accommodating and/or controlling stress/strain incurred during III-N growth on a large diameter silicon substrate. A back-side of a silicon substrate may be processed to adapt substrates of standardized diameters and thicknesses to GOS applications. Bowing and/or warping during high temperature epitaxial growth processes may be mitigated by pre-processing silicon substrate so as to pre-stress the substrate in a manner than counterbalances stress induced by the III-N material and/or improve a substrate's ability to absorb stress. III-N devices fabricated on an engineered GOS substrate may be integrated together with silicon MOS devices fabricated on a separate substrate. Structures employed to improve substrate resilience and/or counterbalance the substrate stress induced by the III-N material may be further employed for interconnecting the III-N and silicon MOS devices of a 3D IC.
申请公布号
WO2016209282(A1)
申请公布日期
2016.12.29
申请号
WO2015US38095
申请日期
2015.06.26
申请人
INTEL CORPORATION
发明人
DASGUPTA, Sansaptak;THEN, Han Wui;RADOSAVLJEVIC, Marko;TOLCHINSKY, Peter, G.;CHAU, Robert, S.