发明名称 BUS SYNCHRONIZED DUPLEX COMPUTER SYSTEM
摘要 <P>PROBLEM TO BE SOLVED: To improve an operation rate of a control object of a bus synchronized duplex computer system. <P>SOLUTION: In a computer system for controlling an operation of a control object from a result of collating, in a collation part 4, respective pieces of data of two arithmetic parts 2A and 2B which synchronously perform the same arithmetic processing to the same information, the bus synchronized duplex computer system includes a standby arithmetic part 3 aside from the two arithmetic parts 2A and 2B, and switches an abnormal side arithmetic part to the standby arithmetic part 3 when the standby arithmetic part 3 is normal and one of the two arithmetic parts 2A and 2B is abnormal from the result of mutually collating, in a different collation part 5, the respective pieces of data of the two arithmetic parts 2A and 2B and the standby arithmetic part 3 before the collation in the collation part 4. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2013101603(A) 申请公布日期 2013.05.23
申请号 JP20120230202 申请日期 2012.10.17
申请人 NIPPON SIGNAL CO LTD:THE;NIHON UNIV 发明人 OGAWA YASUO;OKAMOTO SHOZO;NAKAMURA HIDEO
分类号 G06F11/18 主分类号 G06F11/18
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