| 摘要 |
A signal reception circuit capable of detecting and receiving a signal at a high speed having small amplitude, and a data transfer control device and electronic equipment using the same. A differential pair of reception signals DP and DM is detected by an HS_SQ_L circuit for low speed having high receiving sensitivity and an HS_SQ circuit for high speed having high speed response performance. In the case of a high-speed reception signal, a logical product of a signal HS_DataIn fetched by an HS differential data receiver and a signal HS_SQ indicating the result of signal detection by the HS_SQ circuit for high speed is supplied to a DLL circuit. In the case of a low-speed reception signal, an FS differential receiver is activated after the detection of differential pair of reception signals DP and DM by the HS_SQ_L circuit for low speed. A signal FS_DataIn fetched by the FS differential receiver is supplied to an FS circuit.
|
