发明名称 |
EFFICIENT INSTRUCTION FUSION BY FUSING INSTRUCTIONS THAT FALL WITHIN A COUNTER-TRACKED AMOUNT OF CYCLES APART |
摘要 |
A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction. |
申请公布号 |
US2016246600(A1) |
申请公布日期 |
2016.08.25 |
申请号 |
US201615143522 |
申请日期 |
2016.04.30 |
申请人 |
Ouziel Ido;Rappoport Lihu;Valentine Robert;Gabor Ron;Raghuvanshi Pankaj |
发明人 |
Ouziel Ido;Rappoport Lihu;Valentine Robert;Gabor Ron;Raghuvanshi Pankaj |
分类号 |
G06F9/30;G06F13/40;G06F12/08 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
1. A system comprising:
a plurality of processors; a processor interconnect to communicatively couple two or more of the plurality of processors; a system memory communicatively coupled to one or more of the plurality of processors over a memory interconnect; one of the plurality of processors comprising: a plurality of cores to execute instructions; a cache shared by two or more of the plurality of cores; one of the cores comprising:
an instruction memory to store instructions;a decoder to decode instructions;an instruction fusion circuit to fuse a first instruction and a second instruction to form a fused instruction to be processed by the core as a single instruction; andthe instruction fusion circuit to fuse the first and second instructions when both the first and second instructions have been stored in the instruction memory prior to issuance. |
地址 |
US |