发明名称 |
LOWER-POWER SCRAMBLING WITH IMPROVED SIGNAL INTEGRITY |
摘要 |
An I/O interface supports scrambling, where the scrambling can include nonlinear scrambling of the scrambling code, or dynamic bus inversion of the scrambling code, or selective switching of selected bits of the scrambling code, or a combination of these. The transmitting device includes a scrambler and the receiving device includes a descrambler. Both the scrambler and the descrambler generate a linear feedback scrambling code modified by applying one or more of the techniques mentioned above. The modified scrambling code may cause fewer than half of the scrambled output bits to be toggled with respect to a previous scrambled output. The scrambler applies the modified scrambling code to a signal to transmit. The descrambler applies the modified scrambling code to a received signal. |
申请公布号 |
WO2016105783(A1) |
申请公布日期 |
2016.06.30 |
申请号 |
WO2015US62220 |
申请日期 |
2015.11.23 |
申请人 |
INTEL CORPORATION |
发明人 |
TEOH, EE LOON;OOI, ENG HUN;MOZAK, CHRISTOPHER P.;MCFARLANE, BRIAN R. |
分类号 |
H03M13/00 |
主分类号 |
H03M13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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