发明名称 Differential amplifier circuit
摘要 In one embodiment, a differential amplifier circuit includes a first input terminal, a second input terminal, a first transistor, a second transistor, a third transistor, a current source, a first output terminal, a second output terminal, a first passive element, and a second passive element. The first (second) transistor has a control terminal connected to the first (second) input terminal. The third transistor has a control terminal. The control terminal is applied predetermined bias voltage. The current source is connected to a first terminal in each of the first transistor, second transistor, and third transistor. The first (second) output terminal is connected to a second terminal of the first (second) transistor. The first (second) passive element is connected between the first (second) input terminal and the first (second) output terminal.
申请公布号 US9407221(B2) 申请公布日期 2016.08.02
申请号 US201414528196 申请日期 2014.10.30
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 Itakura Tetsuro;Furuta Masanori;Kimura Shunsuke;Kawata Go;Funaki Hideyuki
分类号 H03F3/45 主分类号 H03F3/45
代理机构 Oblon, McClelland, Maier & Neustadt, L.L.P 代理人 Oblon, McClelland, Maier & Neustadt, L.L.P
主权项 1. A differential amplifier circuit, comprising: a first input terminal; a second input terminal; a first transistor having a control terminal connected to the first input terminal; a second transistor having a control terminal connected to the second input terminal; a third transistor having a control terminal applied predetermined bias voltage; a current source connected to a first terminal of each of the first transistor, the second transistor, and the third transistor; a first output terminal connected to a second terminal of the first transistor; a second output terminal connected to a second terminal of the second transistor; a first passive element connected between the first input terminal and the first output terminal; a second passive element connected between the second input terminal and the second output terminal; and a load circuit connected to the second terminal of each of the first transistor and the second transistor; wherein the load circuit is a current mirror circuit configured to copy current flowing in the third transistor and apply the current to the first transistor and the second transistor.
地址 Minato-ku JP