HIGH SPEED SENSE AMPLIFIER LATCH WITH LOW POWER RAIL-TO-RAIL INPUT COMMON MODE RANGE

摘要

Described is an apparatus which comprises: an input sensing stage for sensing an input signal relative to another signal; a decision making circuit, coupled to the input sensing stage, for determining whether the input signal is a logic low or a logic high; and a power management circuit, coupled to the input sensing stage and the decision making circuit, which is operable to monitor a state of the decision making circuit and to disable the input sensing stage according to the monitored state. Described is an apparatus which comprises: a decision making circuit integrated with an input sensing stage, wherein the decision making circuit is operable to pre-charge its internal nodes during a phase of the clock signal; and a latching circuit to latch an output of the decision making circuit.

主权项

1. An apparatus comprising:
an analog front-end (AFE); and a digital logic coupled to the AFE, wherein the AFE comprises a strong arm latch (SAL) to receive an input signal and to provide an output, wherein the SAL has rail-to-rail common mode range.