Two-dimensional transformation with minimum buffering

摘要

An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) generate a sequence of intermediate matrices by multiplying a sequence of original matrices by a predetermined matrix and (ii) write the intermediate matrices into a memory in a first order that alternates between (a) a first of the intermediate matrices in a row order and (b) a second of the intermediate matrices in a column order. The second circuit may be configured to (i) read the sequence of the intermediate matrices from the memory in a second order that alternates between (a) the first intermediate matrix in the column order and (b) the second intermediate matrix in the row order and (ii) generate a sequence of transform matrices by multiplying the intermediate matrices as read from the memory by another predetermined matrix.

主权项

1. An apparatus comprising:
a first circuit configured to (i) generate a sequence of intermediate matrices by multiplying a sequence of original matrices by a predetermined matrix and (ii) write said intermediate matrices into a memory in a first order that alternates between (a) a first of said intermediate matrices in a row order and (b) a second of said intermediate matrices in a column order; and a second circuit configured to (i) read said sequence of said intermediate matrices from said memory in a second order that alternates between (a) said first intermediate matrix in said column order and (b) said second intermediate matrix in said row order and (ii) generate a sequence of transform matrices by multiplying said intermediate matrices as read from said memory by another predetermined matrix.