发明名称 VITERBI DECODER
摘要 Input operands use two registers R2, R3, upper-level side and lower-level side of the register R2 are compared, and a value selected depending on the comparison results is stored on the upper-level side of another register R4. On the other hand, upper-level side and lower-level side of the register R3 are compared and a value selected depending on the comparison results is stored on the lower-level side of the register R4. Subsequently, data on the upper-level side and lower-level side of the register R4 are read out simultaneously and stored at adjacent addresses on a memory (16) through a bus (17) or (18) of two word width.
申请公布号 WO02056480(A1) 申请公布日期 2002.07.18
申请号 WO2001JP10624 申请日期 2001.12.05
申请人 NEC CORPORATION;IKEKAWA, MASAO 发明人 IKEKAWA, MASAO
分类号 G06F11/10;H03M13/41;H04L1/00;(IPC1-7):H03M13/41 主分类号 G06F11/10
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