LINK ESTABLISHMENT FOR SINGLE PAIR ETHERNET

摘要

A primary device implementing the subject system of link establishment for single pair Ethernet may include at least one processor circuit. The at least one processor circuit may be configured to transmit a first synchronization sequence to a secondary device and to subsequently detect a second synchronization sequence, different than the first, transmitted by the secondary device. The synchronization sequences may be pseudo-noise sequences that have strong autocorrelation characteristics. The at least one processor circuit may be configured to wait a predetermined amount of time after completing the detection of the second synchronization sequence, and then may initiate a training stage. The training stage may include exchanging scrambler states of additive scramblers used by the primary and secondary devices. The at least one processor circuit may be configured to enter a data mode upon completion of training. In the data mode, data is forward error correction encoded and then scrambled.

主权项

1. A primary device comprising:
at least one processor circuit configured to:
transmit a first synchronization sequence to a secondary device;detect a second synchronization sequence transmitted by the secondary device, the second synchronization sequence differing from the first synchronization sequence;wait a first predetermined amount of time after completion of detection of the second synchronization sequence transmitted by secondary device, and then initiating a training stage; andenter a data mode upon completion of the training stage.