| 发明名称 |
CACHE MEMORY SYSTEM AND PROCESSOR SYSTEM |
| 摘要 |
A cache memory includes a first cache memory that is accessible per cache line, and a second cache memory that is accessible per word, the second cache memory being positioned in a same cache layer as the first cache memory. It is achieved to improve an average access speed to the first cache memory and also to improve access efficiency because of data access per word, thereby reducing power consumption. |
| 申请公布号 |
US2016378671(A1) |
申请公布日期 |
2016.12.29 |
| 申请号 |
US201615262635 |
申请日期 |
2016.09.12 |
| 申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
TAKEDA Susumu;FUJITA Shinobu |
| 分类号 |
G06F12/0886;G06F12/0897;G06F12/0842;G06F12/0804;G06F12/0811 |
主分类号 |
G06F12/0886 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A cache memory comprising:
a first cache memory that is accessible per cache line; and a second cache memory that is accessible per word, the second cache memory being positioned in a same cache layer as the first cache memory. |
| 地址 |
Tokyo JP |
