发明名称 |
SEMICONDUCTOR DEVICE INCLUDING CELL REGION STACKED ON PERIPHERAL REGION AND METHOD OF FABRICATING THE SAME |
摘要 |
Provided are semiconductor devices including a peripheral region and a cell region stacked thereon and a method of fabricating the same. The semiconductor device may include a peripheral region including a lower substrate and a peripheral circuit provided thereon and a cell region including an upper substrate and a cell array provided thereon. The cell region may be stacked on the peripheral region. When an operation signal is applied to the cell region from the peripheral region, at least a portion of the peripheral and cell regions may be used as a ground pattern applied with a ground signal, thereby being in an electrical ground state. |
申请公布号 |
US2016307632(A1) |
申请公布日期 |
2016.10.20 |
申请号 |
US201615049526 |
申请日期 |
2016.02.22 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE JAE-EUN;KIM SUNGHOON |
分类号 |
G11C16/14;H01L23/528;H01L21/768;G11C16/04;H01L23/532;H01L27/115;H01L23/522 |
主分类号 |
G11C16/14 |
代理机构 |
|
代理人 |
|
主权项 |
1. A semiconductor device, comprising:
a cell-on-peripheral structure including a peripheral region and a cell region stacked thereon, wherein the peripheral region comprises a lower substrate, a peripheral circuit provided on the lower substrate, and a peripheral metal line electrically connected to the peripheral circuit, wherein the cell region comprises an upper substrate and a cell region overlapping the peripheral circuit, wherein the upper substrate includes a base substrate encompassing junction regions electrically connected to circuits in the cell region; and a grounding structure disposed between the base substrate and the peripheral metal line, the grounding structure providing an electrical ground during a memory cell erase operation. |
地址 |
SUWON-SI KR |