发明名称 Solder bump formation in electronics packaging
摘要 A polymer stencil is applied to the active surface of a wafer. The stencil has openings that at least partially overlay associated metallization pads on the wafer and divider strips positioned between adjacent openings. The divider strips are arranged to overlay portions of associated metallization pads so that at least two adjacent openings overlay portions of each metallization pad. After the stencil has been positioned, a solder paste is applied to the stencil openings. The solder paste may then be reflowed with the polymer stencil remaining in place. The solder naturally creeps under the stencil so that unitary solder bumps are formed on each metallization pad. The described methods and arrangements can be used to create low profile solder bumps that are not attainable using conventional solder bump formation techniques.
申请公布号 US7674702(B1) 申请公布日期 2010.03.09
申请号 US20080104362 申请日期 2008.04.16
申请人 NATIONAL SEMICONDUCTOR CORPORATION 发明人 PATWARDHAN VIRAJ;KELKAR NIKHIL V.
分类号 H01L21/44 主分类号 H01L21/44
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