发明名称 METHOD OF MANUFACTURING SILICON WAFER WITH HIGH PLANARITY
摘要 PROBLEM TO BE SOLVED: To effectively remove a damaged layer generated during a grinding process, to secure high planarity by a minimum amount of polishing in a successive polishing process, and to solve the problem of metallic contamination that can occur during the progress of these processes. SOLUTION: A method of manufacturing a silicon wafer with high-planarity includes: a step (S21) of slicing an ingot of silicon single crystal to produce the wafers; a step (S22) of chamfering the edge of the sliced wafers; a step (S23) of lapping the chamfered wafers; a step (S24) of etching the lapped wafers; a step (S25) of grinding the etched wafers; a step (S26) of slight-etching the wafers by using an alkaline solution, to remove the damaged layer generated in the ground wafers; a step (S27) of polishing both sides or one side of the slight-etched wafers; and a step (S28) of cleaning the polished wafers. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008166805(A) 申请公布日期 2008.07.17
申请号 JP20070337093 申请日期 2007.12.27
申请人 SILTRON INC 发明人 NAM BYUNG-WOOK
分类号 H01L21/304;B24B7/22 主分类号 H01L21/304
代理机构 代理人
主权项
地址